\section{Conclusion} \label{sec:conclusion}

We have demonstrated a methodology that decouples the interconnect
fabric from computing and storage layers, forming a single layer
called ISL, in emerging three-dimensional chip integration
technology. This decoupling can reduce manufacture cost thanks to
smaller die area for each layer in 3D.  It also supports different
manufacture volume for each die in 3D to reduce the overall chip
cost. As an example, we have proposed to superimpose multiple
networks in the interconnect service layer for flexible 3D
integration.  We have extended the state-of-the-art 3D cost model in
this work.  Our evaluation shows that a 3D design with ISL not only
provides significant cost benefits but also achieves
performance-power improvement, compared to its conventional 2D and
3D counterparts.
%Evaluation on other networks and integrating other
%functions in the service layer are considered as future work.
